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STE2002 Datasheet(PDF) 37 Page - STMicroelectronics |
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STE2002 Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 61 page  STE2002 Bus interfaces 37/61 Figure 37. Host processor interconnection with parallel interface Figure 38. application schematic using an external lcd Voltage Generator Figure 39. Application schematic using the internal LCD voltage generator and two separate supplies VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX VDD1 / GND / VSSAUX STE2002 µP VDD1 SA1 SCL SDAIN SDAOUT VDD2 SEL1 SEL2 VSSAUX E PD/C D0 D1 D2 D3 D4 D5 D6 D7 SCLK SCE SD/C SDIN BSY_FLG TEST_6 EXT_SET SA0 RES OSCIN VSSAUX R/W SDOUT ICON_MODE VSSAUX TEST_4 TEST_5 TEST_3 TEST_10 TEST_8 TEST_9 TEST_7 TEST_2 TEST_1 GND / VSSAUX VDD1 VDD1 VDD VDD2 I/O VDD1 VSS2 VSS1 VLCDSENSE VLCDOUT VLCDIN VSS VLCD 81x 128 DISPLAY 40 128 100nF 1 µF 41 VDD2 VDD1 VDD2 I/O VDD1 VSS2 VSS1 VLCDSENSE VLCDOUT VLCDIN VSS 81x 128 DISPLAY 40 128 41 100nF 100nF 1 µF |
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