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STW4811MBRAT/LF Datasheet(PDF) 18 Page - STMicroelectronics |
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STW4811MBRAT/LF Datasheet(HTML) 18 Page - STMicroelectronics |
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18 / 86 page  STw4811M/STw4811N Functional description 17/85 Figure 3. Start-up timing All regulators are started with PDN_regulators or EN_regulators but can be switched off from the beginning or during application by software, ‘pdn_(regulator)’ or ‘en_(regulator)’ bits ( Table 18,Table 24, and Table 25). PON ball PDN__OSC PDN_regulators VDDOK ball CLK32K_IN ball PORn ball PWREN ball OFF START_PM Reset 1ms INT_OSC TCXO_EN ball Internal_OSC 11*(1/32kHz) OFF2 MASTER_CLK ball REQUEST_MC ball VBAT 300µs 9.38ms (11ms wc) Reset START_BIAS 7.77ms (9.46ms wc) “or” Delays are worst case maximum delays Voutput(s) ball VPLL / VIO_VMEM VCORE CLK32K ball (*) (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null |
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