STPD0166BTA3 datasheet(25/48 Pages) STMICROELECTRONICS

25 / 48 page

UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

Issue 1.7 - February 8, 2000

25/48

2.3 UPDATE HISTORY FOR PIN DESCRIPTION CHAPTER

The following changes have been made to the Pin Description Chapter on 08/02/2000

The following changes have been made to the Pin Description Chapter on 13/01/2000

DCLK

Dot Clock / Pixel clock. This clock supplies the display controller, the video pipeline, the ramdac,

and the TV output logic. Its value is dependent on the selected display mode.

Its frequency can be as high as 135 MHz. This signal is either driven by the internal PLL to a minimum of

8MHz or by an external oscillator. The direction can be controlled by a strap option or an internal register

bit.

The following changes have been made to the Pin Description Chapter on 28/09/99

The following changes have been made to the Pin Description Chapter on 23/09/99

The following changes have been made to the Pin Description Chapter on 11/08/99

Removed statement; “The direction can be controlled by a strap option or an internal register bit.”

Section

Change

Text

2.2.3.

Replaced

Signals VIDEO_D[7:0] with VIN, VTV_BT# with ODD_EVEN, VTV_SYNCH with VCS.

Section

Change

Text

2.2.

Added

“

to a minimum of 8MHz”

Section

Change

Text

Table 2-1.

Changed

Updated signal pin counts and added abbreviations to table.

Figure 2-1.

Changed

Updated External interface pin count

Table 2-2.

Replaced

“PWGD” with “SYSRSTI#”

2.2.1.

Moved

PCI_CLKI and PCI_CLKO moved from 2.2.1. to 2.2.5.

2.2.1.

Moved

ISA_CLK and ISA_CLKX2 moved from 2.2.1. to 2.2.8.

2.2.3.

Replaced

“Video Interface” with “Video Input”

Section

Change

Text

2.2.13.

Added

“Note;

By setting signals ST[3:0] to the following value allows the STPC to be put

Tristate. This means the STPC is switched off and no signals are being driven.“

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