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MSC8112 Datasheet(PDF) 1 Page - Freescale Semiconductor, Inc |
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MSC8112 Datasheet(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 44 page  Freescale Semiconductor Data Sheet Document Number: MSC8112 Rev. 0, 5/2008 © Freescale Semiconductor, Inc., 2008. All rights reserved. MSC8112 FC-PBGA–431 20 mm × 20 mm •Two StarCore® SC140 DSP extended cores, each with an SC140 DSP core, 224 Kbyte of internal SRAM M1 memory (448 Kbyte total), 16 way 16 Kbyte instruction cache (ICache), four-entry write buffer, external cache support, programmable interrupt controller (PIC), local interrupt controller (LIC), and low-power Wait and Stop processing modes. • 475 Kbyte M2 memory for critical data and temporary data buffering. • 4 Kbyte boot ROM. • M2-accessible multi-core MQBus connecting the M2 memory to both cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic operation control of M2 memory access by the cores and the local bus. • Internal PLL configured are reset by configuration signal values. • 60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including M1 and M2 memories, and on-device arbitration for up to four master devices. • Direct slave interface (DSI) using a 32/64-bit slave host interface with 21–25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal and external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip ID decoding to allow one CS signal to control multiple DSPs, broadcast mode to write to multiple DSPs, and big-endian/little-endian/munged support. • Three mode signal multiplexing: 64-bit DSI and 32-bit system bus, 32-bit DSI and 64-bit system bus, or 32-bit DSI and 32-bit system bus, and Ethernet port (MII/RMII). • Flexible memory controller with three UPMs, a GPCM, a page-mode SDRAM machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for IPBus peripherals and internal memories. • Multi-channel DMA controller with 16 time-multiplexed single channels, up to four external peripherals, DONE or DRACK protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal FIFOs per channel, FIFO generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the FIFO. • Up to four independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/ μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. • Ethernet controller with support for 10/100 Mbps MII/RMII/SMII including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and VLAN tags and priority, retransmission after collision, CRC generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, VLAN tag insertion, RMON statistics, local bus master DMA for descriptor fetching and buffer access, and optional multiplexing with GPIO (MII/RMII/SMII) or DSI/system bus signals lines (MII/RMII). • UART with full-duplex operation up to 6.25 Mbps. • Up to 32 general-purpose input/output (GPIO) ports. •I2C interface that allows booting from EEPROM devices. • Two timer modules, each with sixteen configurable 16-bit timers. • Eight programmable hardware semaphores. • Global interrupt controller (GIC) with interrupt consolidation and routing to INT_OUT, NMI_OUT, and the cores; twenty-four virtual maskable interrupts (8 per core) and two virtual NMI (one per core) that can be generated by a simple write access. • Optional booting external memory, external host, UART, TDM, or I2C. Dual Core Digital Signal Processor |
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