STV0299B datasheet(12/36 Pages) STMICROELECTRONICS

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STV0299B

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FUNCTIONAL DESCRIPTION (continued)

4.2 Signal Processing

4.2.1

I and Q Inputs

The ADC features differential inputs, but in most

applications I & Q signals are single-ended. In

such applications, I and Q signals from the tuner

are fed to the respective IP and QP inputs through

a capacitor. The IN and QN pins are DC biased,

typically to VBOT.The internal biasing of the ADC is

done on the circuit at the mid-voltage between

VTOP and VBOT.

The

Input/Output

Configuration

described in Address 0Ch.

4.2.2

Main AGC (or AGC1)

The modulus of the I/Q input is compared to a

programmable threshold, m1, and the difference

is integrated. This signal is then converted into a

pulse density modulation signal to drive the AGC

output. It should be filtered by a simple analog

filter to control the gain command of any amplifier

before the A to D converter.

The output converter operates at fM_CLK/8 in order

to decrease the radiated noise and to simplify the

filter design. The output is a 5 V tolerant open

drain stage.

The reset value of the coefficient allows an initial

settling time of less than 100k master clock

periods.

The 8 integrator MSBs may be read or written at

any time by the microprocessor. When written, the

LSB’s are reset and the coefficient may be set to

zero by programming (in this case, the AGC is

reduced

programmable

8-bit

voltage

synthesizer).

The time constant of agc1 is estimated as

followed:

with m1 = AGC1 reference level.

The AGC1 Control, AGC1 Reference and AGC1

Integrator Registers are in Addresses 0D and 0F.

4.2.3

Nyquist Root and Interpolation Filters

Two roll off values are available: 0.35 and 0.20.

Refer to the Input/Output Configuration Register

in Address 0C.

4.2.4

Offset Cancellation

This

device

suppresses

the

residual

component on I and Q. The compensation may be

frozen to its last value by resetting the DC offset

compensation bit in the AGC Control Register in

Address 0D.

4.2.5

Signal AGC (or AGC2)

The rms value of I and Q is measured after the

Nyquist filter and compared to a programmable

value, m2, such as that of the main AGC.

The integrated error signal is applied to a

multiplier on each I and Q path.

The AGC2 Control Register is in Address 10.

Bits [7:5] give the AGC2 coefficient, which sets

beta_agc2, the gain of the integrator. Table 4

shows how beta_agc2 is programmed with AGC2

coefficient (which is related to the time constant of

the AGC).

Table 4:

AGC2

Coefficient = 0,

the

gain

remains

unchanged from its last value.

The time constant is independent of the symbol

frequency, however it does depend on the

modulus, m1, of the input signal, programmed in

AGC1, with the following approximate relation:

The AGC2 Integrator Registers (2 bytes - MSB

and LSB) are in Addresses 18 and 19. These

values

may

read

written

the

microprocessor. When written, all the LSB’s

integrator bits are reset. This value is an image of

the signal power in the useful band. Compared

with the total power of the signal, the out-of-band

power may be computed (noise, or other channel).

agc1

agc 1

–

-----------------------

M_CLK

AGC2 Coefficient

beta_agc2

316

464

256

6N/A

7N/A

Tagc2

M_CLK

⋅

m1 beta_agc2

⋅

---------------------------------------------

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