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STV7617D Datasheet(PDF) 10 Page - STMicroelectronics |
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STV7617D Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 17 page  STV7617, STV7617D, STV7617U 10/17 AC TIMING REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR,tF) = 10 ns) AC TIMING CHARACTERISTICS (VCC =5 V, VPP =90 V, VSSP =0 V, VSSLOG =0 V, VSSSUB =0 V, Tamb =25°C, VILMax. = 0.2 Vcc, VIHMin. =0.8 VCC,VOH = 4.0 V, VOL = 0.4 V, unless otherwise specified) Note 9 See test diagram page 12. Note 10 One output among 64, loading capacitor COUT = 200pF, other outputs at low level. Symbol Parameter Min. Typ. Max. Unit tWHCLK Duration of clock (CLK) pulse at high level 40 - - ns tWLCLK Duration of clock (CLK) pulse at low level 40 - - ns tSDAT Set-up Time of data input before clock (low to high) transition 10 - - ns tHDAT Hold Time of data input after clock (low to high) transition 20 - - ns tDSTB Minimum Delay to latch STB after clock (low to high) transition 25 - - ns tSSTB Set-up Time STB before clock (low to high) transition 10 - - ns tSTB Latch STB Low Level Pulse Duration 20 - - ns tBLK Blanking (BLK) Pulse Duration 500 - - ns tHIZ High Impedance HIZ Pulse Duration 500 - - ns Symbol Parameter Min. Typ. Max. Unit tCLK Data Clock Period 125 - - ns tRDAT Logical Data Output Rise Time - 12 20 ns tFDAT Logical Data Output Fall Time - 10 20 ns tPHL1 tPLH1 Delay of logic data output (high to low transition) after clock (CLK) transition (CL=10pF) Delay of logic data output (low to high transition) after clock (CLK) transition (CL=10 pF) - - 37 42 50 60 ns ns tPHL2 tPLH2 Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition - - 110 115 180 180 ns ns tPHL3 tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition - - 80 95 165 165 ns ns tPHL4 tPLH4 Delay of power output change (high to low transition) to blank (BLK) transition Delay of power output change (low to high transition) to blank (BLK) transition - - 75 75 160 160 ns ns tPHZ5 tPLZ5 Delay of power output change (high to Hi-Z transition) after high impedance (HIZ)(9) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ)(9) - - 40 80 160 160 ns ns tPZH5 tPZL5 Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (9) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (9) - - 75 40 160 160 ns ns tROUT Power Output Rise Time (10) - 175 350 ns tFOUT Power Output Fall Time (10) - 35 150 ns 3 |
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