R8C2K datasheet(95/471 Pages) RENESAS

95 / 471 page

R8C/2K Group, R8C/2L Group

10. Clock Generation Circuit

Rev.1.10

Dec 21, 2007

Page 78 of 450

REJ09B0406-0110

Figure 10.7

Registers FRA2, FRA6 and FRA7

High-Speed On-Chip Oscillator Control Register 2

(1)

Symbol

Address

After Reset

FRA2

0025h

00h

Bit Symbol

Bit Name

Function

NOTE:

1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.

b7 b6 b5 b4 b3 b2 b1 b0

000 00

Selects the dividing ratio for the high-

speed on-chip oscillator clock.

b2 b1 b0

0 0 0: Divide-by-2 mode

0 0 1: Divide-by-3 mode

0 1 0: Divide-by-4 mode

0 1 1: Divide-by-5 mode

1 0 0: Divide-by-6 mode

1 0 1: Divide-by-7 mode

1 1 0: Divide-by-8 mode

1 1 1: Divide-by-9 mode

FRA20

FRA22

—

(b7-b3)

Reserved bits

Set to 0.

High-speed on-chip oscillator

frequency sw itching bits

FRA21

High-Speed On-Chip Oscillator Control Register 6

Symbol

Address

After Reset

FRA6

002Bh

When Shipping

Function

Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction

to match the voltage conditions can be achieved by transferring this value to the FRA1

b3 b2 b1 b0

b7 b6 b5 b4

High-Speed On-Chip Oscillator Control Register 7

Symbol

Address

After Reset

FRA7

002Ch

When Shipping

b7 b6 b5 b4 b3 b2 b1 b0

Function

36.864 MHz frequency correction data is stored.

The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz

by transferring this value to the FRA1 register.

R8C2K Datasheet(PDF) 95 Page - Renesas Technology Corp

R8C2K Datasheet(HTML) 95 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL