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R8C2K Datasheet(PDF) 108 Page - Renesas Technology Corp |
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R8C2K Datasheet(HTML) 108 Page - Renesas Technology Corp |
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108 / 471 page  R8C/2K Group, R8C/2L Group 10. Clock Generation Circuit Rev.1.10 Dec 21, 2007 Page 91 of 450 REJ09B0406-0110 Figure 10.13 shows the State Transitions in Power Control Mode. Figure 10.13 State Transitions in Power Control Mode CM10 = 1 CPU operation stops Stop mode State Transitions in Power Control Mode Reset Wait mode Low-speed on-chip oscillator mode CM14 = 0 OCD2 = 1 FRA01 = 0 High-speed on-chip oscillator mode OCD2 = 1 FRA00 = 1 FRA01 = 1 High-speed clock mode CM05 = 0 CM13 = 1 OCD2 = 0 Standard operating mode CM14 = 0 OCD2 = 1 FRA01 = 0 CM05 = 0 CM13 = 1 OCD2 = 0 CM05 = 0 CM13 = 1 OCD2 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1 FRA00 = 1 FRA01 = 1 CM14 = 0 FRA01 = 0 All oscillators stop Interrupt WAIT instruction Interrupt CM05: Bit in CM0 register CM13, CM14: Bits in CM1 register OCD2: Bit in OCD register FRA00, FRA01: Bits in FRA0 register |
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