HD64F3664FP datasheet(21/444 Pages) RENESAS

21 / 444 page

Rev. 6.00 Mar. 24, 2006 Page xxi of xxviii

Figure 11.2 Increment Timing with Internal Clock .................................................................... 153

Figure 11.3 Increment Timing with External Clock ................................................................... 153

Figure 11.4 OVF Set Timing ...................................................................................................... 153

Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 154

Figure 11.6 TMOV Output Timing ............................................................................................ 154

Figure 11.7 Clear Timing by Compare Match............................................................................ 154

Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 155

Figure 11.9 Pulse Output Example ............................................................................................. 155

Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 156

Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 157

Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 158

Figure 11.13 Internal Clock Switching and TCNTV Operation ................................................. 158

Section 12 Timer W

Figure 12.1 Timer W Block Diagram......................................................................................... 161

Figure 12.2 Free-Running Counter Operation ............................................................................ 172

Figure 12.3 Periodic Counter Operation..................................................................................... 173

Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 173

Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174

Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174

Figure 12.7 Input Capture Operating Example........................................................................... 175

Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 176

Figure 12.9 PWM Mode Example (1) ........................................................................................ 177

Figure 12.10 PWM Mode Example (2) ...................................................................................... 177

Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 178

Figure 12.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 179

Figure 12.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 180

Figure 12.14 Count Timing for Internal Clock Source............................................................... 181

Figure 12.15 Count Timing for External Clock Source.............................................................. 181

Figure 12.16 Output Compare Output Timing ........................................................................... 182

Figure 12.17 Input Capture Input Signal Timing........................................................................ 183

Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 183

Figure 12.19 Buffer Operation Timing (Compare Match).......................................................... 184

Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 184

Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 185

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 186

Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 186

Figure 12.24 Contention between TCNT Write and Clear ......................................................... 187

Figure 12.25 Internal Clock Switching and TCNT Operation.................................................... 188

HD64F3664FP Datasheet(PDF) 21 Page - Renesas Technology Corp