H8SXSLASH1663R datasheet(921/1504 Pages) RENESAS

921 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 889 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

PER

R/(W)* Parity Error

Indicates that a parity error has occurred during reception

in asynchronous mode and the reception ends

abnormally.

[Setting condition]

• When a parity error is detected during reception

Receive data when the parity error occurs is

transferred to RDR, however, the RDRF flag is not

set. Note that when the PER flag is being set to 1, the

subsequent serial reception cannot be performed. In

clocked synchronous mode, serial transmission also

cannot continue.

[Clearing condition]

• When 0 is written to PER after reading PER = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

Even when the RE bit in SCR is cleared, the PER bit

is not affected and retains its previous value.

TEND

Transmit End

[Setting conditions]

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a

transmit character

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When a TXI interrupt request is issued allowing

DMAC or DTC to write data to TDR

MPB

Multiprocessor Bit

Stores the multiprocessor bit value in the receive frame.

When the RE bit in SCR is cleared to 0 its previous state

is retained.

MPBT

R/W

Multiprocessor Bit Transfer

Sets the multiprocessor bit value to be added to the

transmit frame.

Note:

Only 0 can be written, to clear the flag.

H8SX/1663R Datasheet(PDF) 921 Page - Renesas Technology Corp

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