H8SXSLASH1663R datasheet(1012/1504 Pages) RENESAS

1012 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 980 of 1468

REJ09B0412-0200

20.3.13

EP1 Data Register (EPDR1)

EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,

and has a capacity of twice the maximum packet size. When one packet of data is received

successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is

indicated in the EP1 receive data size register. After the data has been read, the buffer that was

read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The

receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized

by means of EP1CLR in the FCLR register.

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

D7 to D0

All 0

Data register for endpoint 1 transfer

20.3.14

EP2 Data Register (EPDR2)

EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,

and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO

buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the

dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by

DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register.

Bit

Bit Name

Initial Value

R/W

Undefined

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

D7 to D0

Undefined W

Data register for endpoint 2 transfer

H8SX/1663R Datasheet(PDF) 1012 Page - Renesas Technology Corp

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