H8SXSLASH1663R datasheet(1019/1504 Pages) RENESAS

1019 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 987 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

EP2DMAE

R/W

Endpoint 2 DMA Transfer Enable

When this bit is set, DMA transfer is enabled from

memory to the endpoint 2 transmit FIFO buffer. If

there is at least one byte of open space in the FIFO

buffer, a DMAC start interrupt signal (USBINTN1) is

asserted. In DMA transfer, when 64 bytes are written

to the FIFO buffer the EP2 packet enable bit is set

automatically, allowing 64 bytes of data to be

transferred, and if there is still space in the other side

of the two FIFOs, the DMAC start interrupt signal

(USBINTN1) is asserted again. However, if the size of

the data packet to be transmitted is less than 64

bytes, the EP2 packet enable bit is not set

automatically, and so should be set by the CPU with a

DMA transfer end interrupt.

As EP2-related interrupt requests to the CPU are not

automatically masked, interrupt requests should be

masked as necessary in the interrupt enable register.

• Operating procedure

1. Write of 1 to the EP2 DMAE bit in DMAR

2. Set the DMAC to activate through USBINTN1

3. Transfer count setting in the DMAC

4. DMAC activation

5. DMA transfer

6. DMA transfer end interrupt generated

See section 20.8.3, DMA Transfer for Endpoint 2.

H8SX/1663R Datasheet(PDF) 1019 Page - Renesas Technology Corp