H8SXSLASH1663R datasheet(1063/1504 Pages) RENESAS

1063 / 1504 page

Section 20 USB Function Module (USB)

Rev. 2.00 Sep. 24, 2008 Page 1031 of 1468

REJ09B0412-0200

20.10.4

Assigning Interrupt Sources to EP0

The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must

be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.

20.10.5

Clearing the FIFO When DMA Transfer is Enabled

The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is

enabled (EP1 DMAE in DMAR = 1). Cancel DMA transfer before clearing the register.

20.10.6

Notes on TR Interrupt

Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,

EP2, or EP3.

The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent

from the USB host. However, at the timing shown in figure 20.26, multiple TR interrupts occur

successively. Take appropriate measures against malfunction in such a case.

Note:

This module determines whether to return NAKC if the FIFO of the target EP has no data

when receiving the IN token, but the TR interrupt flag is set after a NAKC handshake is

sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is

set again.

CPU

Host

IN token

Sets TR flag

(Sets the flag again)

Sets TR flag

Determines whether

to return NACK

Transmits data

TR interrupt routine

Clear

TR flag

Writes

transmit data

TRG.

PKTE

TR interrupt routine

USB

NACK

Determines whether

to return NACK

NACK

ACK

Figure 20.26 TR Interrupt Flag Set Timing

H8SX/1663R Datasheet(PDF) 1063 Page - Renesas Technology Corp

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