H8SXSLASH1663R datasheet(1077/1504 Pages) RENESAS

1077 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1045 of 1468

REJ09B0412-0200

21.3.5

2C Bus Status Register (ICSR)

ICSR confirms the interrupt request flags and status.

Bit

Bit Name

Initial Value

R/W

TDRE

R/W

TEND

R/W

RDRF

R/W

NACKF

R/W

STOP

R/W

AAS

R/W

ADZ

R/W

Bit

Bit Name

Initial

Value

R/W

Description

TDRE

R/W

Transmit Data Register Empty

[Setting condition]

• When data is transferred from ICDRT to ICDRS

and ICDRT becomes empty

• When the TRS bits are set

• When the start (re-transmit included) condition has

been issued

• When switched from reception to transmission in

slave mode

[Clearing conditions]

• When 0 is written to this bit after reading TDRE = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

• When data is written to ICDRT

TEND

R/W

Transmit End

[Setting condition]

• When the ninth clock of SCL rises while the TDRE

flag is 1

[Clearing conditions]

• When 0 is written to this bit after reading TEND = 1

(When the CPU is used to clear this flag by writing

0 while the corresponding interrupt is enabled, be

sure to read the flag after writing 0 to it.)

• When data is written to ICDRT

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