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H8SX/1663R Datasheet(PDF) 1080 Page - Renesas Technology Corp

Part # H8SX/1663R
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datasheet(HTML) 1080 Page - Renesas Technology Corp

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Section 21 I
2C Bus Interface 2 (IIC2)
Rev. 2.00 Sep. 24, 2008 Page 1048 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
Value
R/W
Description
0
ADZ
0
R/W
General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
• When the general call address is detected in slave
receive mode
[Clearing condition]
• When 0 is written to this bit after reading ADZ = 1
21.3.6
Slave Address Register (SAR)
SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of
the first frame received after a start condition, the LSI operates as the slave device.
Bit
Bit Name
Initial Value
R/W
7
SVA6
0
R/W
6
SVA5
0
R/W
5
SVA4
0
R/W
4
SVA3
0
R/W
3
SVA2
0
R/W
2
SVA1
0
R/W
1
SVA0
0
R/W
0
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1
SVA6 to
SVA0
0
R/W
Slave Address 6 to 0
These bits set a unique address differing from the
addresses of other slave devices connected to the I
2C
bus.
0
0
R/W
Reserved
Although this bit is readable/writable, only 0 should be
written to.



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