H8SXSLASH1663R datasheet(1085/1504 Pages) RENESAS

1085 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1053 of 1468

REJ09B0412-0200

21.4.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data from the slave

device, and returns an acknowledge signal. Figures 21.7 and 21.8 show the operation timings in

master receive mode. The reception procedure and operations in master receive mode are shown

below.

1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master

transmit mode to master receive mode. Then, clear the TDRE bit to 0.

2. When ICDDR is read (dummy read), reception is started, the receive clock pulse is output, and

data is received, in synchronization with the internal clock. The master mode outputs the level

specified by the ACKBT in ICIER to SDA, at the ninth receive clock pulse.

3. After the reception of the first frame data is completed, the RDRF bit in ICSR is set to 1 at the

rising of the ninth receive clock pulse. At this time, the received data is read by reading

ICDRR. At the same time, RDRF is cleared.

4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time

RDRF is set. If the eighth receive clock pulse falls after reading ICDRR by other processing

while RDRF is 1, SCL is fixed to a low level until ICDRR is read.

5. If the next frame is the last receive data, set the RCVD bit in ICCRA before reading ICDRR.

This enables the issuance of the stop condition after the next reception.

6. When the RDRF bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition

is issued.

7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RCVD to 0.

8. The operation returns to the slave receive mode.

H8SX/1663R Datasheet(PDF) 1085 Page - Renesas Technology Corp