H8SXSLASH1663R datasheet(1087/1504 Pages) RENESAS

1087 / 1504 page

Section 21 I

2C Bus Interface 2 (IIC2)

Rev. 2.00 Sep. 24, 2008 Page 1055 of 1468

REJ09B0412-0200

SDA

(Master output)

SDA

(Slave output)

RDRF

RCVD

ICDRS

ICDRR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCL

(Master output)

Data n-1

Data n

Data n-1

Data n

User

processing

[8] Set slave receive mode

[5] Set RCVD then read ICDRR

[6] Issue stop condition

[7] Read ICDRR and clear RCVD

Figure 21.8 Master Receive Mode Operation Timing 2

21.4.4

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, and the master device outputs

the receive clock pulse and returns an acknowledge signal. Figures 21.9 and 21.10 show the

operation timings in slave transmit mode. The transmission procedure and operations in slave

transmit mode are described below.

1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the

WAIT in ICMR and CKS3 to CKS0 in ICCRA(initial setting). Set the MST and TRS bits in

ICCRA to select slave receive mode, and wait until the slave address matches.

2. When the slave address matches in the first frame following the detection of the start

condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the

rising of the ninth clock pulse. At this time, if the eighth bit data (R/

W) is 1, TRS in ICCRA

and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically.

The continuous transmission is performed by writing the transmit data to ICDRT every time

TDRE is set.

3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to

1, with TDRE = 1. When TEND is set, clear TEND.

4. Clear TRS for end processing, and read ICDRR (dummy read) to release SCL.

5. Clear TDRE.

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