H8SXSLASH1663R datasheet(1104/1504 Pages) RENESAS

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Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1072 of 1468

REJ09B0412-0200

22.3.1

A/D Data Registers A to H (ADDRA to ADDRH)

There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of

A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown

in table 22.2.

The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0.

The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read

directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit

units.



Bit

Bit Name

Initial Value

R/W

Table 22.2

Analog Input Channels and Corresponding ADDR Registers

A/D Data Register Storing Conversion Result

Analog

Input

Channel

Unit 0

Unit 1*

AN0

ADDRA_0 (Unit 0)



AN1

ADDRB_0 (Unit 0)



AN2

ADDRC_0 (Unit 0)



AN3

ADDRD_0 (Unit 0)



AN4

ADDRE_0 (Unit 0)*

ADDRE_1 (Unit 1)*

AN5

ADDRF_0 (Unit 0)*

ADDRF_1 (Unit 1)*

AN6

ADDRG_0 (Unit 0)*

ADDRG_1 (Unit 1)*

AN7

ADDRH_0 (Unit 0)*

ADDRH_1 (Unit 1)*

Notes: 1. A/D conversion should be not performed on the same channel by multiple units.

2. The ADDRA_1 to ADDRD_1 registers for unit 1 are not used.

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