H8SXSLASH1663R datasheet(1263/1504 Pages) RENESAS

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Section 27 Clock Pulse Generator

Rev. 2.00 Sep. 24, 2008 Page 1231 of 1468

REJ09B0412-0200

27.6

Usage Notes

27.6.1

Notes on Clock Pulse Generator

1. The following points should be noted since the frequency of

φ (Iφ: system clock, Pφ:

peripheral module clock, B

φ: external bus clock) supplied to each module changes according

to the setting of SCKCR.

Select a clock division ratio that is within the operation guaranteed range of clock cycle time

cyc shown in the AC timing of electrical characteristics.

Since I

φ min = 8MHz, Pφ min = 8MHz, Bφ min = 8MHz,

φ max = 50 MHz, P φ max = 35 MHz, and Bφ max = 50 MHz,

the frequencies should satisfy the conditions 8 MHz

≤ Iφ ≤ 50 MHz, 8 MHz ≤ Pφ ≤ 35 MHz,

and 8 MHz

≤ Bφ ≤ 50 MHz.

2. All the on-chip peripheral modules (except for the EXDMAC, DMAC, and DTC) operate on

the P

φ. Note therefore that the time processing of modules such as a timer and SCI differs

before and after changing the clock division ratio.

In addition, wait time for clearing software standby mode differs by changing the clock

division ratio. For details, see section 28.7.3, Setting Oscillation Settling Time after Exit from

Software Standby Mode.

3. The relationship among the system clock, peripheral module clock, and external bus clock is I

≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,

φ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits

PCK2 to PCK0 or BCK2 to BCK0.f

4. Note that the frequency of

φ will be changed in the middle of a bus cycle when setting SCKCR

or SUBCKCR while executing the external bus cycle with the write-data-buffer function and

EXDMAC.

5. Figure 27.9 shows the clock modification timing. After a value is written to SCKCR, this LSI

waits for the current bus cycle to complete. After the current bus cycle completes, each clock

frequency will be modified within one cycle (worst case) of the external input clock

φ.

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