H8SXSLASH1663R datasheet(1318/1504 Pages) RENESAS

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Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1286 of 1468

REJ09B0412-0200

28.12.6

Control of Input Buffers by DIRQnE (n = 3 to 0)

When the input buffers for the P10/

IRQ0-A to P13/IRQ3-A pins are enabled by setting the

DIRQnE bits (n = 3 to 0) in DSPIER to 1, the PnICR settings corresponding to these pins are

invalid. Therefore, note that external inputs to these pins, of which states are reflected on the

DIRQnF bits, are also input to the interrupt controller, peripheral modules and I/O ports, after the

DIRQnE bits (n = 3 to 0) are set to 1.

28.12.7

Conflict between a transition to deep standby mode and interrupts

If a conflict among the transition to deep software standby mode and generation of software

standby mode clearing source occurs, a transition to deep software standby mode is not made but

the software standby mode clearing sequence is executed. In this case, an interrupt exception

handling for the input interrupt starts after the oscillation settling time for software standby mode

(set by the STS4 to STS0 bits in SBYCR) has elapsed.

Note that if a conflict between a deep software standby mode transition and NMI interrupt occurs,

the NMI interrupt exception handling routine is required.

If a conflict among a deep software standby mode transition, the IRQ0 to IRQ11 interrupts, 32K

timer interrupt, and voltage-monitoring interrupt* occurs, a transition to deep software standby

mode can be made without executing the interrupt execution handling by clearing the SSIn bits in

SSIER to 0 beforehand.

Note: * Supported only by the H8SX/1668M Group

28.12.8

φ/SDRAMφ Output State

φ/SDRAMφ output is undefined for a maximum of one cycle immediately after deep software

standby mode is canceled with the IOKEEP bit cleared to 0 or immediately after the IOKEEP bit

is cleared after cancellation of deep software standby mode with the IOKEEP bit set to 1.

However, B

φ/SDRAMφ can be normally output by setting the IOKEEP, PSTOP1, and PSTP0 bits

to 1. For details, see section 28.8.4, B

φ/SDRAMφ Operation after Exit from Deep Software

Standby Mode.

H8SX/1663R Datasheet(PDF) 1318 Page - Renesas Technology Corp