H8SXSLASH1663R datasheet(1474/1504 Pages) RENESAS

1474 / 1504 page

Main Revisions and Additions in this Edition

Rev. 2.00 Sep. 24, 2008 Page 1442 of 1468

REJ09B0412-0200

Item

Page

Revision (See Manual for Details)

Section 25 Flash Memory

25.7.1 Programming/Erasing

Interface Registers

1120

Added

Bit 0 R/W*

Note: This is a write-only bit. This bit is always read as 0.

25.7.2 Programming/Erasing

Interface Parameters

(3) Flash Program/Erase

Frequency Parameter

(FPEFEQ)

1132

Amended

FPEFEQ sets the operating frequency of the CPU. The

operating frequency available in this LSI ranges from 8 MHz

to 50 MHz.

Amended

5. Do not turn off the Vcc power supply nor remove the chip

from the PROM programmer during programming/erasure

in which a high voltage is applied to the flash memory.

Doing so may damage the flash memory permanently. If

a reset is input, the reset must be released after the reset

input period of at least 100µs.

25.14 Usage Notes

1203

Amended

7. At powering on the Vcc power supply, fix the RES pin to

low and set the flash memory to hardware protection

state. This power on timing must also be satisfied at a

power-off and power-on caused by a power failure and

other factors.

Section 26 Boundary Scan

26.4.3 Boundary Scan

1210

Amended

Table 26.4

Table item "from TDI" is added.

"from TDI" and "to TDO" are deleted from the pin name of

the table item

Section 27 Clock Pulse

Generator

27.6.1 Notes on Clock Pulse

Generator

1231

Amended

Item numbers 1 to 5 are added

4. Note that the frequency of f will be changed in the middle

of a bus cycle when setting SCKCR0 or SUBCKCR while

executing the external bus cycle with the write-data-buffer

function and EXDMAC

Section 28 Power-Down

Modes

28.2 Register Descriptions

1239

Amended

•

Deep standby backup register n (DPSBKRn)

(n=15 to 0)

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