H8SXSLASH1663R datasheet(1472/1504 Pages) RENESAS

1472 / 1504 page

Main Revisions and Additions in this Edition

Rev. 2.00 Sep. 24, 2008 Page 1440 of 1468

REJ09B0412-0200

Item

Page

Revision (See Manual for Details)

Section 18 Watchdog Timer

(WDT)

18.3.2 Timer Control/Status

858

Added

The description below for the bit 7 in the bit table is added:

(When the CPU is used to clear this flag while the

corresponding interrupt is enabled, be sure to read the flag

after writing 0 to it.)

Section 19 Serial

Communication Interface

(SCI, IrDA, CRC)

19.3.12 IrDA Control Register

(IrCR)

911

Amended

The description below for the bit 7 in the bit table

1.TxD5/IrTxD and RxD5/IrRxD pins are operate as IrTxD

and IrRxD.

Section 21 I

2C Bus Interface 2

(IIC2)

21.1 Features

1033

Added

Module stop function setting

1047

Deleted

The description below for the bit 1 is deleted:

[Clearing condition]

When 0 is written to this bit after reading AAS = 1 (When

the CPU is used to clear this flag by writing 0 while the

corresponding interrupt is enabled, be sure to read the flag

after writing 0 to it.)

21.3.5 I

2C Bus Status

1048

Deleted

The description below for the bit 0 is deleted:

[Clearing condition]

When 0 is written to this bit after reading ADZ = 1 (When

the CPU is used to clear this flag by writing 0 while the

corresponding interrupt is enabled, be sure to read the flag

after writing 0 to it.)

21.7 Usage Notes

1066

Added

6. Setting of the module stop function

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