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H8SX/1663M Datasheet(PDF) 516 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 516 Page - Renesas Technology Corp |
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516 / 1504 page  Section 11 EXDMA Controller (EXDMAC) Rev. 2.00 Sep. 24, 2008 Page 484 of 1468 REJ09B0412-0200 LSI Data flow External address bus External data bus EXDMAC EDACK EDREQ External memory External device with DACK Figure 11.4 Data Flow in Single Address Mode EXDMA cycle EDSAR Address for external memory space RD signal to external memory space Data output by external memory Address bus B φ RD WR EDACK ETEND Data bus EXDMA cycle EDDAR Address for external memory space WR signal to external memory space B φ Address bus Transfer from external memory to external device with DACK RD WR EDACK ETEND Data bus Data output from external device with DACK Transfer from external device with DACK to external memory High High Figure 11.5 Example of Timing in Single Address Mode |
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