Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

Preview PDF HTML

H8SX/1663M Datasheet(PDF) 947 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 947 Page - Renesas Technology Corp

Back Button H8SX/1663M Datasheet HTML 943Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 944Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 945Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 946Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 947Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 948Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 949Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 950Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 951Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 947 / 1504 page
background image
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 915 of 1468
REJ09B0412-0200
19.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to
the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/
A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the
clock frequency should be 16 times the bit rate (when ABCS
= 0) and 8 times the bit rate (when
ABCS
= 1).
In addition, when an external clock is specified, the average transfer rate or the base clock of
TMR_4 to TMR_7 can be selected by the ACS3 to ACS0 bits in SEMR_5 and SEMR_6.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 19.7.
0
1 frame
D0
D1
D2
D3
D4
D5
D6
D7
0/1
11
SCK
TxD
Figure 19.7 Phase Relation between Output Clock and Transmit Data
(Asynchronous Mode)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com