H8SXSLASH1663M datasheet(963/1504 Pages) RENESAS

963 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 931 of 1468

REJ09B0412-0200

19.6.3

Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)

Figure 19.19 shows an example of the operation for transmission in clocked synchronous mode. In

transmission, the SCI operates as described below.

1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.

Because the TXI interrupt processing routine writes the next transmit data to TDR before

transmission of the current transmit data has finished, continuous transmission can be enabled.

3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output

mode has been specified and synchronized with the input clock when use of an external clock

has been specified.

4. The SCI checks the TDRE flag at the timing for sending the last bit.

5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and

serial transmission of the next frame is started.

6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the

output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request

is generated. The SCK pin is fixed high.

Figure 19.20 shows a sample flowchart for serial data transmission. Even if the TDRE flag is

cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.

Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the

RE bit to 0 does not clear the receive error flags.

H8SX/1663M Datasheet(PDF) 963 Page - Renesas Technology Corp