H8SXSLASH1663M datasheet(964/1504 Pages) RENESAS

964 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 932 of 1468

REJ09B0412-0200

Transfer direction

Bit 0

Serial data

Synchronization

clock

1 frame

TDRE

TEND

Data written to TDR

and TDRE flag cleared

to 0 in TXI interrupt

processing routine

TXI interrupt

request generated

Bit 1

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

TXI interrupt

request generated

TEI interrupt request

generated

Figure 19.19 Example of Operation for Transmission in Clocked Synchronous Mode

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR

[2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE = 1

All data transmitted

TEND = 1

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI state check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0. However, the TDRE

flag is checked and cleared

automatically when the DMAC or

DTC is initiated by a transmit data

empty interrupt (TXI) request and

writes data to TDR.

Figure 19.20 Sample Serial Transmission Flowchart

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