H8SXSLASH1663M datasheet(980/1504 Pages) RENESAS

980 / 1504 page

Section 19 Serial Communication Interface (SCI, IrDA, CRC)

Rev. 2.00 Sep. 24, 2008 Page 948 of 1468

REJ09B0412-0200

(1)

Transmission

During transmission, the output signals from the SCI (UART frames) are converted to IR frames

using the IrDA interface (see figure 19.37).

For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is

output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in

IrCR.

The high-level pulse width is defined to be 1.41

µs at minimum and (3/16 + 2.5%) × bit rate or

(3/16

× bit rate) +1.08 µs at maximum. For example, when the frequency of system clock φ is 20

MHz, a high-level pulse width of 1.6 µs can be specified because it is the smallest value in the

range greater than 1.41 µs.

For serial data of level 1, no pulses are output.

UART frame

Data

IR frame

Data

000

Transmission

Reception

Bit

cycle

Pulse width is 1.6

µs to

3/16 bit cycle

Start

bit

Stop

bit

Stop

bit

Start

bit

Figure 19.37 IrDA Transmission and Reception

(2)

Reception

During reception, IR frames are converted to UART frames using the IrDA interface before

inputting to SCI. 0 is output when the high level pulse is detected while 1 is output when no pulse

is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41

µs is also regarded as a 0 signal.

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