H8SXSLASH1663M datasheet(1105/1504 Pages) RENESAS

1105 / 1504 page

Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1073 of 1468

REJ09B0412-0200

22.3.2

A/D Control/Status Register for Unit 0 (ADCSR_0)

ADCSR_0 controls A/D conversion operations.

ADF

R/(W)*

ADIE

R/W

ADST

R/W

CH3

R/W

CH2

R/W

CH1

R/W

CH0

R/W

Bit

Bit Name

Initial Value

R/W

Note: * Only 0 can be written to this bit, to clear the flag.

Bit

Bit Name

Initial

Value

R/W

Description

ADF

R/(W)* A/D End Flag

A status flag that indicates the end of A/D conversion.

[Setting conditions]

• Completion of A/D conversion in single mode

• Completion of A/D conversion on all specified

channels in scan mode

[Clearing conditions]

• Writing of 0 after reading ADF = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• Reading from ADDR after activation of the DMAC or

DTC by an ADI interrupt

ADIE

R/W

A/D Interrupt Enable

Setting this bit to 1 enables ADI interrupts by ADF.

ADST

R/W

A/D Start

Clearing this bit to 0 stops A/D conversion, and the A/D

converter enters wait state.

Setting this bit to 1 starts A/D conversion. In single mode,

this bit is cleared to 0 automatically when A/D conversion

on the specified channel ends. In scan mode, A/D

conversion continues sequentially on the specified

channels until this bit is cleared to 0 by software, a reset,

or hardware standby mode.

Note: Do not write to ADST when activation is by an

external trigger. For details, see section 22.7.3,

Notes on A/D activation by an External Trigger.



R/W

Reserved

This bit is always read as 0. The write value should

always be 0.

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