H8SXSLASH1663M datasheet(1117/1504 Pages) RENESAS

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Section 22 A/D Converter

Rev. 2.00 Sep. 24, 2008 Page 1085 of 1468

REJ09B0412-0200

22.4.3

Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input when the A/D conversion start delay time (t

D) passes after the ADST bit in ADCSR is set to

1, then starts A/D conversion. Figure 22.6 shows the A/D conversion timing. Tables 22.3 and 22.4

show the A/D conversion time.

As shown in figure 22.6, the A/D conversion time (t

CONV) includes the A/D conversion start delay

time (t

D) and the input sampling time (tSPL). The length of tD varies depending on the timing of the

write access to ADCSR. The total conversion time therefore varies within the ranges indicated in

tables 22.3 and 22.4.

In scan mode, the values given in tables 22.3 and 22.4 apply to the first conversion time. The

values given in table 22.5 apply to the second and subsequent conversions. In either case, bits

CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated

by the A/D conversion characteristics.

(1)

(2)

tSPL

tCONV

Address

Write signal

Input sampling

timing

ADF

[Legend]

(1):

ADCSR write cycle

(2):

ADCSR address

tD:

A/D conversion start delay time

tSPL:

Input sampling time

tCONV: A/D conversion time

Figure 22.6 A/D Conversion Timing

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