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H8SX/1663M Datasheet(PDF) 1157 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1157 Page - Renesas Technology Corp

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Section 25 Flash Memory
Rev. 2.00 Sep. 24, 2008 Page 1125 of 1468
REJ09B0412-0200
25.7.2
Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, storage place for
program data, start address of programming destination, and erase block number, and exchanges
the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the
on-chip RAM area. The initial values of programming/erasing interface parameters are undefined
at a reset or a transition to software standby mode.
Since registers of the CPU except for ER0 and ER1 are saved in the stack area during download of
an on-chip program, initialization, programming, or erasing, allocate the stack area before
performing these operations (the maximum stack size is 128 bytes). The return value of the
processing result is written in R0. The programming/erasing interface parameters are used in
download control, initialization before programming or erasing, programming, and erasing. Table
25.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and
fail result parameter (FPFR) varies in initialization, programming, and erasure.
Table 25.4
Parameters and Target Modes
Parameter
Download
Initialization
Programming
Erasure
R/W
Initial
Value
Allocation
DPFR
O
R/W
Undefined
On-chip RAM*
FPFR
O
O
O
O
R/W
Undefined
R0L of CPU
FPEFEQ
O
R/W
Undefined
ER0 of CPU
FMPAR
O
R/W
Undefined
ER1 of CPU
FMPDR
O
R/W
Undefined
ER0 of CPU
FEBS
O
R/W
Undefined
ER0 of CPU
Note:
*
A single byte of the start address of the on-chip RAM specified by FTDAR
(a)
Download Control
The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-
chip RAM area to download the on-chip program is the 4-Kbyte area starting from the start
address specified by FTDAR. Download is set by the programming/erasing interface registers, and
the download pass and fail result parameter (DPFR) indicates the return value.



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