H8SXSLASH1663M datasheet(1161/1504 Pages) RENESAS

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Section 25 Flash Memory

Rev. 2.00 Sep. 24, 2008 Page 1129 of 1468

REJ09B0412-0200

(b)

Programming

FPFR indicates the return value of the programming result.



Bit

Bit Name

Bit

Bit Name

Initial

Value

R/W

Description



Unused

Returns 0.



R/W

Programming Mode Related Setting Error Detect

Detects the error protection state and returns the result.

When the error protection state is entered, this bit is set

to 1. Whether the error protection state is entered or not

can be confirmed with the FLER bit in FCCS. For

conditions to enter the error protection state see section

25.9.3, Error Protection.

0: Normal operation (FLER = 0)

1: Error protection state, and programming cannot be

performed (FLER = 1)



R/W

Programming Execution Error Detect

Writes 1 to this bit when the specified data could not be

written because the user MAT was not erased. If this bit

is set to 1, there is a high possibility that the user MAT

has been written to partially. In this case, after removing

the error factor, erase the user MAT. If FMATS is set to

H'AA and the user boot MAT is selected, an error occurs

when programming is performed. In this case, both the

user MAT and user boot MAT have not been written to.

Programming the user boot MAT should be performed in

boot mode or programmer mode.

0: Programming has ended normally

1: Programming has ended abnormally (programming

result is not guaranteed)

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