H8SXSLASH1663M datasheet(1240/1504 Pages) RENESAS

1240 / 1504 page

Section 26 Boundary Scan

Rev. 2.00 Sep. 24, 2008 Page 1208 of 1468

REJ09B0412-0200

26.4.1

Instruction Register (JTIR)

JTIR is a 16-bit register. JTAG instructions can be transferred to JTIR by serial input from the

TDI pin. JTIR is initialized when the

TRST signal is low level, when the TAP controller is in the

Test-Logic-Reset state, and when this LSI is placed in hardware standby mode. JTIR is not

initialized by a reset or entry to software standby mode. Instructions must be serially transferred in

4-bit units. When an instruction with more than 4 bits is being transferred, the last four bits of the

serial data are stored in JTIR.

Bit

Bit Name

Initial Value

R/W

TS3



TS2



TS1



TS0



Bit

Bit Name

Initial Value

R/W



Bit

Bit Name

Initial

Value

R/W

Descriptions

15 to 12 TS[3:0]

All 0

R/W

Test Bit Set

Specify an instruction as shown in table 26.3.

11 to 0



All 0

Reserved

These bits are always read as 0. The write value should

always 0.

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