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H8SX/1663M Datasheet(PDF) 1296 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1296 Page - Renesas Technology Corp |
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1296 / 1504 page ![]() Section 28 Power-Down Modes Rev. 2.00 Sep. 24, 2008 Page 1264 of 1468 REJ09B0412-0200 Table 28.2 Oscillation Settling Time Setting P φ* (MHz) STS4 STS3 STS2 STS1 STS0 Standby Time 35 25 20 13 10 8 Unit 0 Reserved 0 1 Reserved 0 Reserved 0 1 1 Reserved 0 Reserved 0 1 64 1.8 2.6 3.2 4.9 6.4 8.0 0 512 14.6 20.5 25.6 39.4 51.2 64.0 0 1 1 1 1024 29.3 41.0 51.2 78.8 102.4 128.0 0 2048 58.5 81.9 102.4 157.5 204.8 256.0 µs 0 1 4096 0.12 0.16 0.20 0.32 0.41 0.51 0 16384 0.47 0.66 0.82 1.26 1.64 2.05 0 1 1 32768 0.94 1.31 1.64 2.52 3.28 4.10 0 65536 1.87 2.62 3.28 5.04 6.55 8.19 0 1 131072 3.74 5.24 6.55 10.08 13.11 16.38 0 262144 7.49 10.49 13.11 20.16 26.21 32.77 0 1 1 1 1 524288 14.98 20.97 26.21 40.33 52.43 65.54 1 0 0 0 0 Reserved ms [Legend] : Recommended setting when external clock is in use : Recommended setting when crystal oscillator is in use Note: * P φ is the output from the peripheral module frequency divider. The oscillation settling time, which includes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. The above figures are for reference. |
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