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H8SX/1663M Datasheet(PDF) 1292 Page - Renesas Technology Corp

Part # H8SX/1663M
Description  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1292 Page - Renesas Technology Corp

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Section 28 Power-Down Modes
Rev. 2.00 Sep. 24, 2008 Page 1260 of 1468
REJ09B0412-0200
28.4
Module Stop State
Module stop functionality can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module
operation stops at the end of the bus cycle and a transition is made to a module stop state. The
CPU continues operating independently.
When the corresponding MSTP bit is cleared to 0, a module stop state is cleared and the module
starts operating at the end of the bus cycle. In a module stop state, the internal states of modules
other than the SCI are retained.
After the reset state is cleared, all modules other than the EXDMAC, DMAC, and DTC and on-
chip RAM are placed in a module stop state.
The registers of the module for which the module stop state is selected cannot be read from or
written to.
28.5
Sleep Mode
28.5.1
Entry to Sleep Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep
mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are
retained. Other peripheral functions do not stop.
28.5.2
Exit from Sleep Mode
Sleep mode is exited by any interrupt, signals on the
RES or STBY pin, and a reset caused by a
watchdog timer overflow, a voltage monitoring reset*, or a power-on reset*.
• Exit from sleep mode by interrupt
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exit from sleep mode by RES pin
Setting the
RES pin level low selects the reset state. After the stipulated reset input duration,
driving the
RES pin high makes the CPU start the reset exception processing.
• Exit from sleep mode by STBY pin
When the
STBY pin level is driven low, a transition is made to hardware standby mode.



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