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H8SX/1663M Datasheet(PDF) 1303 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1303 Page - Renesas Technology Corp |
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1303 / 1504 page ![]() Section 28 Power-Down Modes Rev. 2.00 Sep. 24, 2008 Page 1271 of 1468 REJ09B0412-0200 28.8.5 Setting Oscillation Settling Time after Exit from Deep Software Standby Mode The WTSTS5 to WTSTS0 bits in DPSWCR should be set as follows: 1. Using a crystal resonator Specify the WTSTS5 to WTSTS0 bits so that the standby time is at least equal to the oscillation settling time. Table 28.3 shows EXTAL input clock frequencies and the standby time according to WTSTS5 to WTSTS0 settings. 2. Using an external clock The PLL circuit settling time should be considered. See table 28.3 to set the standby time. |
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