H8SXSLASH1663M datasheet(1316/1504 Pages) RENESAS

1316 / 1504 page

Section 28 Power-Down Modes

Rev. 2.00 Sep. 24, 2008 Page 1284 of 1468

REJ09B0412-0200

28.11

φ Clock Output Control

Output of the

φ clock (Bφ/SDφ) can be controlled by bits PSTOP1 and PSTOP0 in SCKCR, and

DDR for the corresponding port. Bits PSTOP1 control the B

φ clock output on the PA7 pin. Bit

PSTOP0 controls the SD

φ clock output on the PB7 pin. When bit PSTOP1 is set to 1, the Bφ clock

output stops at the end of the bus cycle and goes high. In the same way, bit PSTOP0 drives the

φ clock output on the PB7 pin high. When DDR for the PA7 pin is cleared to 0, the Bφ clock

output is disabled and the pin becomes an input port. When the SDRAM interface is disabled, the

PB7 pin can be used as I/O port.

Tables 28.4 and 28.5 show the states of the

φ pin in each processing state.

Table 28.4

φ Pin (PA7) State in Each Processing State

Software

Standby Mode

Deep Software

Standby Mode

DDR

PSTOP1

Normal

Operating

Mode

Sleep

Mode

All-

Module-

Clock-Stop

Mode

OPE = 0

OPE = 1

IOKEEP = 0

IOKEEP = 1

Hardware

Standby

Mode

Hi-Z

φ output

φ output Bφ output

High

Hi-Z

High

Hi-Z

[Legend]

x = Don't care

Table 28.5

φ Pin (PB7) State in Each Processing State (When SDRAM Interface is

Enabled)

Software

Standby Mode

Deep Software

Standby Mode

PSTOP0

Normal

Operating

Mode

Sleep

Mode

All-

Module-

Clock-Stop

Mode

OPE = 0

OPE = 1

IOKEEP = 0

IOKEEP = 1

Hardware

Standby

Mode

φ output SDφ

output

φ output High

High

Hi-Z

High

Hi-Z

H8SX/1663M Datasheet(PDF) 1316 Page - Renesas Technology Corp

H8SX/1663M Datasheet(HTML) 1316 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL