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H8SX/1663M Datasheet(PDF) 1438 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1438 Page - Renesas Technology Corp |
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1438 / 1504 page  Section 30 Electrical Characteristics Rev. 2.00 Sep. 24, 2008 Page 1406 of 1468 REJ09B0412-0200 EDRAK0 to EDRAK3 tEDRKD tEDRKD B φ Figure 30.41 EXDMAC, EDRAK Timing 30.4.5 Timing of On-Chip Peripheral Modules Table 30.10 Timing of On-Chip Peripheral Modules Conditions: V CC = PLLVCC = DrVCC = 3.0 V to 3.6 V* 2, AV CC = 3.0 V to 3.6 V, Vref = 3.0 V to AV CC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Pφ = 8 MHz to 35 MHz, T a = –20°C to +75°C (regular specifications), T a = –40°C to +85°C (wide-range specifications) Item Symbol Min. Max. Unit Test Conditions Output data delay time t PWD 40 ns Figure 30.42 Input data setup time t PRS 25 ns I/O ports Input data hold time t PRH 25 ns Timer output delay time t TOCD 40 ns Figure 30.43 Timer input setup time t TICS 25 ns Timer clock input setup time t TCKS 25 ns Figure 30.44 Single-edge setting t TCKWH 1.5 t cyc TPU Timer clock pulse width Both-edge setting t TCKWL 2.5 t cyc PPG Pulse output delay time t POD 40 ns Figure 30.45 |
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