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H8SX/1663M Datasheet(PDF) 1440 Page - Renesas Technology Corp |
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H8SX/1663M Datasheet(HTML) 1440 Page - Renesas Technology Corp |
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1440 / 1504 page ![]() Section 30 Electrical Characteristics Rev. 2.00 Sep. 24, 2008 Page 1408 of 1468 REJ09B0412-0200 Item Symbol Min. Max. Unit Test Conditions Stop condition input setup time t STOS 1 t cyc + 20 ns Data input setup time t SDAS 0 ns Data input hold time t SDAH 0 ns SCL, SDA capacitive load Cb 400 pF IIC2 SCL, SDA falling time t Sf 300 ns Figure 30.53 TCK clock cycle time t TCKcyc 50* 1 ns Figure 30.54 Boundary scan TCK clock high level pulse width t TCKH 20 ns TCK clock low level pulse width t TCKL 20 ns TCK clock rising time t TCKr 5 ns TCK clock falling time t TCKf 5 ns TRST pulse width t TRSTW 20 Tcyc Figure 30.55 TMS setup time t TMSS 20 ns Figure 30.56 TMS hold time t TMSH 20 ns TDI setup time t TDIS 20 ns TDI hold time t TDIH 20 ns TDI data delay time t TDOD 23 ns Notes: 1. t TCKcyc ≥ tTCKcyc 2. V CC = PLLVCC = DrVCC = 2.95 V to 3.60 V in the H8SX/1668M Group. T1 tPRS tPRH tPWD T2 P φ Ports 1 to 3, 5, 6, A, to F, H, I, M, J, K (read) Ports 1 to 3, 6, A to F, H, I,M, J, K (write) Figure 30.42 I/O Port Input/Output Timing |
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