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M32C/86 Datasheet(PDF) 436 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 436 Page - Renesas Technology Corp |
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436 / 505 page  Page 413 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 25. Flash Memory Version ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Table 25.5 Status Register D0 to D7: These data buses are read when the read status register command is executed. NOTES: 1. The FMR07 (SR5) and FMR06 (SR4) bits are set to "0" by executing the clear status register command. When the FMR07 (SR5) or FMR06 (SR4) bit is set to "1", the program, block erase, erase all unlocked block and lock bit program commands are not accepted. Bits in SRD register SR4 (D4) SR5 (D5) SR7 (D7) SR6 (D6) Status Name Definition SR1 (D1) SR2 (D2) SR3 (D3) SR0 (D0) Program status Erase status Sequencer status Reserved bit Reserved bit Reserved bit Reserved bit "1" READY - - - - - "0" BUSY - - - - - Reserved bit Bits in FMR0 Register FMR00 FMR07 FMR06 Value after Reset 1 0 0 Successfully completed Successfully completed - - - - - Error Error (1) (1) |
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