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M32C/86 Datasheet(PDF) 286 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 286 Page - Renesas Technology Corp |
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286 / 505 page  Page 263 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figures 22.1 shows a block diagram of the intelligent I/O. Figure 22.2 shows a block diagram of the intelligent I/O communication. Figure 22.1 Intelligent I/O Block Diagram G1TM0, G1PO0 Register(1) G1TM1, G1PO1 Register(1) G1TM2, G1PO2 Register(1) G1TM3, G1PO3 Register(1) G1TM4, G1PO4 Register(1) G1TM5, G1PO5 Register(1) G1TM6, G1PO6 Register(1) G1TM7, G1PO7 Register(1) Base Timer Base timer reset in the communication unit 1 Request by matching the base timer with the G1PO0 register Request from the INT pin Divider 2(n+1) DIV4 to DIV0 fBT1 Edge Select Digital Filter Edge Select Gate Function Gate Function Edge Select Edge Select Edge Select Edge Select Edge Select Edge Select INPC10 BCK1 and BCK0 11 10 00 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 10 : fBT1 11 : f1 00 00 00 00 00 00 00 INPC11 / ISCLK1 INPC12 / ISRxD1 INPC13 INPC14 INPC15 INPC16 INPC17 BTS BTRE DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 DF1 and DF0 CTS1 and CTS0 GT GT 1 1 0 0 1 1 0 0 PR PR Ch0 to Ch7 interrupt request signal OUTC10/ISTxD1 /BE1OUT OUTC11/ISCLK1 OUTC14 OUTC12 OUTC13 OUTC15 OUTC16 OUTC17 Prescaler Function Prescaler Function Overflow of bit 15 in the base timer Overflow of bit 9 in the base timer f1 111 000 to 010 111 000 to 010 MOD2 to MOD0 MOD2 to MOD0 DIV4 to DIV0 bits, BCK1 and BCK0 bits : Bits in the G1BCR0 Register BTS : Bit in the G1BCR1 Register CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj Register (j = 0 to 7) MOD2 to MOD0 : Bits in the G1POCRj Register BTRE : Bit in the G1POCR0 Register NOTES: 1. Each register is placed in a reset state after the G1BCR0 register supplies the clock. Communication Unit 1 Communication Unit 0 ISRxD0 ISTxD0 ISCLK0 f8 f2n f1 Two-phase pulse signal is applied 0 1 Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter Digital Filter PWM Output PWM Output PWM Output PWM Output |
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