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M32C/86 Datasheet(PDF) 287 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 287 Page - Renesas Technology Corp |
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287 / 505 page  Page 264 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Reception Transmission Arbitration Special Interrupt Check Buffer Register Shift Register Start Bit Generation Circuit Bit Insert Circuit SOF Generation Circuit Stop Bit Generation Circuit Transmit Latch Transmit Data Generation Circuit Clock Wait Control Circuit Transmit Register Transmit Buffer Transmit Register Transmit Buffer Receive Register Receive Buffer Receive Data Generation Circuit Start Bit Check Bit Insert Check Stop Bit Check G1RI Register Receive Register Receive Buffer HDLC Data Receive Interrupt Request Transmit Interrupt Request Receive Interrupt Request Special Communication Interrupt Request Comparator (8bit) Comparator (8bit) Comparator (8bit) Comparator G1CMP0 Register (8bit) G1CMP0 Register (8bit) G1CMP0 Register (8bit) G1CMP3 Register G1RB Register G1TO Register G1TB Register (Transmit Buffer Register) G1DR Register (Receive Data Register) G1TCRC Register G1RCRC Register Data Selector Data Selector Reception 10 11 ISCLK0 ISRxD0 ISTxD0 Comparator Comparator Comparator Comparator G0CMP0 register G0CMP0 register G0CMP0 register G0CMP3 Register Buffer Register Shift Register Bit Insert Circuit SOF Generation Circuit Transmit Latch Transmit Data Generation Circuit G0TCRC Register Data Selector Clock Wait Control Circuit Transmit Register Transmit Buffer G0TO Register Transmit Register Transmit Buffer G0RB Register Receive Register Receive Buffer Receive Data Generation Circuit Bit Insert Check G0RCRC Register G0RI Register CCS1 and CCS0 Receive Register Receive Buffer Communication Unit 0 Communication Unit 1 HDLC Data Receive Interrupt Request HDLC Data Transmit Interrupt Request Transmit Interrupt Request SIO0TR(1) G0TOR(1) SIO0RR(1) SRT0R(1) G0RIR(1) HDLC Data Transmit Interrupt Request Receive Interrupt Request Special Communication Interrupt Request Transmission G0DR Register (Receive Data Register) f2n f8 01 f1 G0TB Register (Transmit Buffer Register) Data Selector TXSL 1 0 RXSL 1 0 CKDIR 1 0 Arbitration ISCLK1 ISRxD1 CKDIR 1 0 f2n f8 10 11 00 CCS3 and CCS2 f1 01 RXSL 1 0 TXSL 1 0 CKDIR : Bit in the GiMR Register (i=0,1) TXSL, RXSL : Bits in the GiEMR Register CCS1 and CCS0 : Bits in the CCS Register Polarity Inverse Generated Clock in the Channel i (i=1 to 3) Transmit Operation Clock Receive Operation Clock Polarity Inverse ISTxD1 Special Interrupt Check Transmit Operation Clock Receive Operation Clock SIO1TR(1) G1TOR(1) G1RIR(1) SIO1RR(1) SRT1R(1) NOTES: 1. See Figure 11.14. Figure 22.2 Intelligent I/O Communication Block Diagram |
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