M32CSLASH86 datasheet(294/505 Pages) RENESAS

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22. Intelligent I/O (Base Timer)

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22.1 Base Timer

The base timer is a free-running counter that counts an internally generated count source.

Table 22.2 lists specifications of the base timer. Figures 22.3 and 22.4 show registers associated with the

base timer. Figure 22.9 shows a block diagram of the base timer. Figure 22.10 shows an example of the

base timer in counter increment mode. Figure 22.11 shows an example of the base timer in counter incre-

ment/decrement mode. Figure 22.12 shows an example of two-phase pulse signal processing mode.

Table 22.2 Base Timer Specifications

Item

Specification

Count Source (fBT1)f1 divided by

2(n+1) , two-phase pulse input divided by 2(n+1)

n: determined by the DIV4 to DIV0 bits in the G1BCR0 register

n=0 to 31; however no division when n=31

Counting Operation

The base timer increments the counter value

The base timer increments and decrements the counter value

Two-phase pulse signal processing

Counter Start Condition

The BTS bit in the G1BCR1 register is set to "1" (base timer starts counting)

Counter Stop Condition

The BTS bit in the G1BCR1 register is set to "0" (base timer reset)

Base Timer Reset Condition

• The value of the base timer matches the value of the G1PO0 register

________

_______

• An low-level ("L") signal is applied to the INT0 or INT1 pin

• Bit 15 or bit 9 in the base timer overflows

Value when the Base Timer is Reset

"000016"

Interrupt Request

The BT1R bit in the IIO4IR register is set to "1" (interrupt requested) when bit

9, bit 14 or bit 15 in the base timer overflows (See Figure 11.14.)

Read from Base Timer

• The G1BT register indicates the counter value while the base timer is running

• The G1BT register is indeterminate when the base timer is reset

Write to Base Timer

When a value is written while the base timer is running, the timer counter

immediately starts counting from this value. No value can be written while

the base timer is reset

Selectable Function

• Counter increment/decrement mode

The base timer starts counting when the BTS bit is set to "1". After

reaching to "FFFF16", the timer counter is then decremented back to

"000016". If the RST1 bit in the G1BCR1 register is set to "1" (the base

timer is reset by matching with the G1PO0 register), the timer counter

starts decrementing in two counts after the base timer matches the G1PO0

timer counter reaches "000016." (See Figure 22.11.)

• Two-phase pulse processing mode

Two-phase pulse signals from P76 and P77 pins or P80 and P81 pins

are counted as well. (See Figure 22.12.)

The IPSA_0 bit in the IPSA register controls input pin selection.

(Refer to 24. Programmable I/O Ports)

The timer increments

counter on all edge

The timer decrements

counter on all edges

P80

(P76)

P81

(P77)

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