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M32C/86 Datasheet(PDF) 298 Page - Renesas Technology Corp |
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M32C/86 Datasheet(HTML) 298 Page - Renesas Technology Corp |
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298 / 505 page ![]() Page 275 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 22. Intelligent I/O (Base Timer) ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M Figure 22.12 Base Timer Operation in Two-phase Pulse Signal Processing Mode (1) When the base timer is reset while the base timer increments the counter value (2) When the base timer is reset while the base timer decrements the counter value m Base TImer min 1 µs (Note 1) min 1 µs m+1 1 2 0 Set to "0" in this timing The base timer starts counting P80 (P76) (2) (A-phase) P81 (P77) (2) (B-phase) INT1 (Z-phase) Set to "1" in this timing min 1 µs (Note 1) min 1 µs mm-1 FFFF16 FFFE16 0 Set to "0" in this timing NOTES: 1. 1.5 fBT1 clock cycles or more are required. 2. Select either port by setting the IPSA_0 bit in the IPSA register. The base timer starts counting Set to "FFFF16" in this timing Input Waveform ( ) When selects no division with the divider by 2(n+1) "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" "H" "L" fBT1 Base TImer P80 (P76) (2) (A-phase) P81 (P77) (2) (B-phase) INT1 (Z-phase) Input Waveform When selects no division with the divider by 2(n+1) fBT1 "H" "L" ( ) |
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