7220 datasheet(11/303 Pages) RENESAS

11 / 303 page

7220 Group User’s Manual

List of figures

CHAPTER 1. OVERVIEW

Fig. 1.2.1 Pin configuration (top view) (1) ................................................................................. 1-5

Fig. 1.2.2 Pin configuration (top view) (2) ................................................................................. 1-6

Fig. 1.4.1 Functional block diagram ............................................................................................ 1-9

CHAPTER 2. FUNCTIONAL DESCRIPTION

Fig. 2.1.1 Registers configuration diagram ................................................................................ 2-2

Fig. 2.1.2 CPU mode register ...................................................................................................... 2-3

Fig. 2.1.3 Sequence of push onto/pop from a stack during interrupts and

subroutine calls ............................................................................................................ 2-5

Fig. 2.1.4 Contents of stack after execution of BRK instruction ............................................. 2-7

Fig. 2.2.1 Access area of M37221M4-XXXSP and M37221M6-XXXSP/FP ........................... 2-8

Fig. 2.2.2 Access area of M37221M8-XXXSP and M37221MA-XXXSP ................................. 2-9

Fig. 2.3.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............ 2-11

Fig. 2.3.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP .................. 2-12

Fig. 2.3.3 Memory map of SFR (special function register) (1) ............................................. 2-13

Fig. 2.3.4 Memory map of SFR (special function register) (2) ............................................. 2-14

Fig. 2.3.5 Memory map of 2 page register (only M37221M8-XXXSP and

M37221MA-XXXSP) ................................................................................................... 2-15

Fig. 2.3.6 I/O setting example of port ...................................................................................... 2-16

Fig. 2.3.7 Access to timer registers .......................................................................................... 2-18

Fig. 2.4.1 I/O pin block diagram (1) ......................................................................................... 2-24

Fig. 2.4.2 I/O pin block diagram (2) ......................................................................................... 2-25

Fig. 2.5.1 VSYNC interrupt generation timing .............................................................................. 2-27

Fig. 2.5.2 Interrupt control logic ................................................................................................ 2-29

Fig. 2.5.3 Interrupt request register 1 (address 00FC16) ........................................................ 2-30

Fig. 2.5.4 Interrupt request register 2 (address 00FD16) ........................................................ 2-30

Fig. 2.5.5 Interrupt control register 1 (address 00FE16) ......................................................... 2-31

Fig. 2.5.6 Interrupt control register 2 (address 00FF16) .......................................................... 2-31

Fig. 2.5.7 Interrupt input polatiry register (address 00F916) ................................................... 2-32

Fig. 2.5.8 CRT port control register (address 00EC16) ........................................................... 2-32

Fig. 2.5.9 Interrupt control system ............................................................................................ 2-33

Fig. 2.5.10 Interrupt vector table ............................................................................................... 2-33

Fig. 2.6.1 Timer 1, timer 2, timer 3, and timer 4 block diagram .......................................... 2-34

Fig. 2.6.2 Timer overflow timing ................................................................................................ 2-35

Fig. 2.6.3 Timer 12 mode register (address 00F416) .............................................................. 2-36

Fig. 2.6.4 Timer 34 mode register (address 00F516) .............................................................. 2-37

Fig. 2.6.5 Example of timer system .......................................................................................... 2-38

Fig. 2.7.1 Serial I/O block diagram ........................................................................................... 2-41

Fig. 2.7.2 Serial I/O mode register (address 00DC16) ............................................................ 2-41

Fig. 2.7.3 Serial input/output common transfer mode block diagram ................................... 2-42

Fig. 2.7.4 Serial I/O register when receiving (when SM5 = “0”) ........................................... 2-43

Fig. 2.7.5 Serial I/O register when transmitting (when SM5 = “0”) ...................................... 2-44

Fig. 2.7.6 Timing diagram of serial I/O .................................................................................... 2-45

Fig. 2.7.7 Connection example for serial I/O transmit/receive .............................................. 2-46

Fig. 2.7.8 Serial data transmit/receive processing sequence ................................................ 2-46

7220 Datasheet(PDF) 11 Page - Renesas Technology Corp

7220 Datasheet(HTML) 11 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL