7733 datasheet(98/940 Pages) RENESAS

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7733 Group User's Manual

4–19

INTERRUPTS

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4.10 External interrupts (INTi interrupt)

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An external interrupt request occurs by input signal from pin INTi (i = 0 to 2). The occurrence condition of

an external interrupt request can be selected by the level sense/edge sense selection bit and the polarity

selection bit (bits 5 and 4 at addresses 7D16 to 7F16) shown in Figure 4.10.2. Table 4.10.1 lists the

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occurrence condition of INTi interrupt request.

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When using pins P62/INT0 to P64/INT2 as external interrupt input pins, set their corresponding bits at address

1016 (Port P6 direction register) to “0.” (Refer to “Figure 4.10.1.”) These pins can be pulled high by

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software. (Refer to section “3.3 Pull-up function of P62 to P64 pins (INT0 to INT2).”

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The INT2 interrupt is invalid when the key input interrupt selection bit (bit 7 at address 6D16) = “1.” (Refer

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to chapter “5 KEY INPUT INTERRUPT FUNCTION.”) When using the INT2 interrupt function, clear the key

input interrupt selection bit to “0.”

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A signal which is input to pin INTi requires a “H”/“L”-level duration of 250 ns or more independent of the

system clock frequency (Note 1).

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Note that even when pins P62/INT0 to P64/INT2 are used as external interrupt input pins, these pins’ state

can be read in by reading bits 2 to 4 at address E16 (Port P6 register).

Note 1: When the falling edge or “L” level is selected as the interrupt occurrence condition, make sure that

“L”-level duration must be at least 250 ns: when the rising edge or “H” level is selected as the

interrupt occurrence condition, make sure that “H”-level duration must be at least 250 ns.

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4.10 External interrupts (INTi interrupt)

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Table 4.10.1 Occurrence condition of INTi interrupt request

b5 (Note 2)

b4 (Note 2)

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Note 2: “b5” and “b4” represent bits 5 and 4 of the INT0 to INT2/key input interrupt control register. (Refer

to “Figure 4.10.2.”)

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In an INTi interrupt, pin INTi’s state is always checked, and then an interrupt request is generated

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according to the state. Therefore, when an INTi interrupt is not used, clear the INTi interrupt’s

priority level to “0.”

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INTi

interrupt request occurrence condition

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Occurs at the falling edge of an input signal to pin INTi (Edge sense).

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Occurs at the rising edge of an input signal to pin INTi (Edge sense).

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Occurs when pin INTi is at “H” level (Level sense).

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Occurs when pin INTi is at “L” level (Level sense).

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