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TDA7580 Datasheet(PDF) 16 Page - STMicroelectronics |
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TDA7580 Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 31 page ![]() TDA7580 16/31 SAI INTERFACE Figure 3. SAI Timings Note TDSP = DSP master clock cycle time = 1/FDSP Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 Timing Description Value Unit TDSP Internal DSP Clock Period (Typical 1/74.1MHz) 13.495 ns tsckr Minimum Clock Cycle 32*TDSP ns tdt SCKR active edge to data out valid 40 ns tlrs LRCK setup time 16 ns tlrh LRCK hold time 9 ns tsdid SDI setup time 16 ns tsdih SDI hold time 9 ns tsckph Minimum SCK high time 0.5*tsckr ns tsckpl Minimum SCK low time 0.5*tsckr ns tsckr tsckpl tdt tsdis tlrs tsckph tlrh tsdih Valid LRCKR SDI0-1 SCKR Valid (RCKP=0) RIGHT LEFT SCKR SDI0-1 LRCKR LSB(n-1) MSB(n) MSB-1(n) MSB-2(n) |
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