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ADE5169 Datasheet(PDF) 13 Page - Analog Devices |
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ADE5169 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 148 page  ADE5166/ADE5169 Rev. 0 | Page 13 of 148 Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters Parameter Description Min Typ Max Unit t SS SS to SCLK edge 145 ns tSL SCLK low pulse width 6 × tCORE1 ns tSH SCLK high pulse width 6 × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge 2 × tCORE1+ 0.5 μs μs tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns tDOSS Data output valid after SS edge 0 ns tSFS SS high after SCLK edge 0 ns 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 25); tCORE = 2CD/4.096 MHz. MSB MOSI BITS [6:1] tDHD tDSU LSB IN BITS [6:1] LSB tDR tDF tDAV MISO tSR tSS SCLK (SPICPOL = 1) SCLK (SPICPOL = 0) SS tSF tSFS tSL tSH tDOSS MSB IN Figure 7. SPI Slave Mode Timing (SPICPHA = 0) |
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