CY25562
Document Number: 38-07392 Rev. *C
Page 4 of 8
SSCG
SSCG uses a patented technology of modulating the clock over
a very narrow bandwidth and controlled rate of change, both
peak and cycle-to-cycle. CY25562 takes a narrow band digital
reference clock in the range of 50 to 200 MHz and produces a
clock that sweeps between a controlled start (F1) and stop (F2)
frequency at a precise rate of change. To understand what
happens to a clock when SSCG is applied, consider a 200 MHz
clock with a 50 percent duty cycle, as shown in this figure.
Clock frequency = fc = 200 MHz
Clock period = Tc = 1/200 MHz
If this clock is applied to the Xin/CLK pin of CY25562, the output
clock at pin 4 (SSCLK) sweeps back and forth between two
frequencies. These two frequencies, F1 and F2, calculate total
amount of spread or bandwidth applied to the reference clock at
pin 1. As the clock is making the transition, sweep, from F1 to
F2, the amount of time and sweep waveform become a very
important factor in the amount of EMI reduction realized from an
SSCG clock.
The modulation domain analyzer is used to visualize the sweep
waveform and sweep period. Figure 3 shows the modulation
profile of a 200 MHz SSCG clock. Notice that the actual sweep
waveform is not a simple sine or sawtooth waveform. Figure 3
also shows a scan of the same SSCG clock using a spectrum
analyzer. The spectrum analyzer scan shows a 10 dB reduction
in the peak RF energy when using CY25562 SSCG clock.
Modulation Rate
Spread spectrum clock generators use frequency modulation
(FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (Fmax) and minimum
frequency of the clock (Fmin) determine this band of frequencies.
The time required to transition from Fmin to Fmax and back to
Fmin is the period of the modulation rate, Tmod. Modulation
rates of SSCG clocks are generally referred to in terms of
frequency or Fmod = 1/Tmod.
The input clock frequency, Fin, and the internal divider count,
Cdiv, determine the modulation rate. In some SSCG clock gener-
ators, the selected range determines the internal divider count.
In other SSCG clocks, the internal divider count is fixed over the
operating range of the part. CY25562 has a fixed divider count
of 2332.
Figure 3. SSCG Clock, Part Number, Fin = 200 MHz
Tc = 5.0 ns
50 %
50 %
Device
Cdiv
CY25562
2332
(All Ranges)
Example:
Device =
CY25562
Fin
=
200 MHz
Range =
S1 = 1, S0 = 1
Then;
Modulation Rate = Fmod = 200 MHz/2332 = 85.7 kHz.
Modulation Profile
Spectrum Analyzer
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