CS47048 Data Sheet

Audio SOC Processor Family

DS787A7

Copyright 2008 Cirrus Logic

11

The second 8-Channel SRC is a stand-alone digital-to-digital conversion module. It can be used to

make independent input clock domains synchronous (different Fs on PCM input and S/PDIF Rx) or

to drive the S/PDIF Tx at a different Fs than the PCM output of the DSP.

modes. Master/Slave operation is chosen by mode select pins when the CS47048 comes out of

reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock

speed must always be

≤ (DSP Core Frequency/2)). The CS47048 serial control port also includes

a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate when the

DSP has a message for the host (SCP_IRQ).

4.3.9 GPIO

Many of the CS47048 peripheral pins are multiplexed with GPIO. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active-low, or active-high.

4.3.10 PLL-based Clock Generator

The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used

to clock the DSP core and peripherals. Through a second PLL divider chain, a dependent clock

domain can be output on the DAO port for driving audio converters. The CS47048 defaults to

running from the external reference frequency and is switched to use the PLL output after overlays

have been loaded and configured, either through master boot from an external FLASH or through

host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered

output frequency ratio is selectable between 1:1 (default) or 2:1.

4.3.11 Hardware Watchdog Timer

The CS47048 has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset.

This peripheral ensures that the CS47048 will reset itself in the event of a temporary system failure.

In stand-alone mode (i.e. no host MCU), the DSP will reboot from external FLASH. In slave mode

(i.e. host MCU present) a GPIO will be used to signal the host that the watchdog has expired and

the DSP should be rebooted and re-configured.

4.4 DSP I/O Description

4.4.1 Multiplexed Pins

Many of the CS47048 pins are multi-functional. For details on pin functionality please refer to the

CS47048 System Designer’s Guide.

4.4.2 Termination Requirements

Open-drain pins on the CS47048 must be pulled high for proper operation. Please refer to the

CS47048 System Designer’s Guide to identify which pins are open-drain and what value of pull-up

resistor is required for proper operation.

Mode select pins on the CS47048 are used to select the boot mode upon the rising edge from

reset. A detailed explanation of termination requirements for each communication mode select pin

can be found in the CS47048 System Designer’s Guide.

4.4.3 Pads

The CS47048 Digital I/Os operate from the 3.3 V supply and are 5 V tolerant.