AT25DF321 datasheet(22/37 Pages) ATMEL

22 / 37 page

3669A–DFLASH–07/07

AT25DF321

• Write Disable operation completes successfully

• Write Status Register operation completes successfully or aborts

• Protect Sector operation completes successfully or aborts

• Unprotect Sector operation completes successfully or aborts

• Byte/Page Program operation completes successfully or aborts

• Block Erase operation completes successfully or aborts

• Chip Erase operation completes successfully or aborts

If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts

due to an incomplete or unrecognized opcode being clocked into the device before the CS pin is

deasserted. In order for the WEL bit to be reset when an operation aborts prematurely, the entire

opcode for a program, erase, Protect Sector, Unprotect Sector, or Write Status Register com-

mand must have been clocked into the device.

10.1.6

RDY/BSY Bit

The RDY/BSY bit is used to determine whether or not an internal operation, such as a program

or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase

cycle, new Status Register data must be continually clocked out of the device until the state of

the RDY/BSY bit changes from a logical “1” to a logical “0”.

Figure 10-1. Read Status Register

10.2

Write Status Register

The Write Status Register command is used to modify the SPRL bit of the Status Register

and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis-

ter command can be issued, the Write Enable command must have been previously issued to

set the WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode

of 01h must be clocked into the device followed by one byte of data. The one byte of data con-

sists of the SPRL bit value, a don't care bit, four data bits to denote whether a Global Protect or

Unprotect should be performed, and two additional don’t care bits (see Table 10-2). Any addi-

tional data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the

SPRL bit in the Status Register will be modified and the WEL bit in the Status Register will be

reset back to a logical “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before

the Write Status Register command was executed (the prior state of the SPRL bit) will determine

whether or not a Global Protect or Global Unprotect will be perfomed. Please refer to the “Global

Protect/Unprotect” section on page 15 for more details.

SCK

MSB

00000101

410 11

812

21 22

15 16

13 14

23 24

OPCODE

MSB

DDDDDD

MSB

DDDDD

STATUS REGISTER DATA

HIGH-IMPEDANCE

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